1. Field of the Invention
This invention relates to integrated circuit processing and, more particularly, to a process for depositing a non-conductive barrier layer such as a nitride film onto a copper surface.
2. Description of the Related Art
A high density integrated circuit typically comprises numerous electrical devices and conductors formed on multiple layers of conducting and semiconducting material that are deposited and patterned in sequence onto a substrate surface. Additionally, insulating material is typically positioned between the individual devices so as to electrically isolated the devices from one another. In particular, intermediate insulating layers, better known as interlevel dielectrics (ILDs), are typically interposed between conducting layers in a circuit so as to electrically isolate components formed on adjacent layers. The insulating layers inhibit electrical shorts and preserve device integrity.
An integrated circuit is operable when its individual components are interconnected with an external source and with one another. In particular, designs of more complex circuits often involve electrical interconnections between components on different layers of the circuit as well as between devices formed on the same layer. Such electrical interconnections between components are typically established through electrical contacts formed on the individual components. The contacts provide an exposed conductive surfaces on each device where electrical connections can be made. However, in a multilayer, high density integrated circuit, the components are often buried in internal sublayers of the circuit where insulating material are deposited over the components making the establishment of electrical contacts difficult.
One method of creating electrical contacts on devices located in the sublayers of the circuit is by forming openings in the interlevel dielectrics (ILDs) that are deposited over the components. The openings, known as contact vias or holes, typically extend downwardly from a top surface of the ILD to the layer containing the electrical devices so that a top surface of the device is exposed. Furthermore, the openings are then filled with a conductive material, such as copper, which effectively establishes electrical contact for components located underneath the ILD.
In addition to contact vias, trenches can also be etched onto the surface of the insulating material in a desired pattern for a conductor layer in a process that is commonly known as the damascene process. In a typical damascene process, the trenches are etched on the surface of the insulating material comprising an ILD and subsequently metalized so as to produce integrated conductors. In particular, the trenches are metalized in a similar manner as that of the contact vias wherein the trenches are filled with a conductive material so as to establish a desired conductive path.
The metalization process generally involves depositing a layer of conductive material such as copper into the vias or trenches, thereby interconnecting electrical devices and wiring at various levels. In a multilayer integrated circuit assembly, an insulating layer is typically deposited onto the metalized vias or trenches so as to electrically isolated the metalized vias or trenches from additional circuit layers that will be formed in a stacked configuration above the vias or trenches. In particular, the insulating layer typically comprises an oxide material such as silicon dioxide wherein the oxide electrically isolates devices formed on adjacent circuit layers. Disadvantageously, however, the oxide layer will lose its insulating properties when copper or other conductive material diffuses from the underlying adjacent layer into the oxide layer. In particular, metal that migrates into an insulating oxide layer can effectively short out the devices electrically isolated by the layer.
To address this problem, a non-conductive barrier layer is generally interposed between the conductive layer and the adjacent insulating layer wherein the barrier layer inhibits metal from diffusing into the insulating layer. In particular, a non-conductive barrier layer typically comprises a nitride film and is preferably positioned between a top surface of a copper wiring layer and a bottom surface of an adjacent oxide layer so as to inhibit copper from migrating upwardly into the oxide layer. Furthermore, the nitride film can be deposited onto the copper surface by using well known deposition techniques such as evaporation, sputtering, chemical vapor deposition, or plasma enhanced chemical vapor deposition (PECVD).
However, one disadvantage of the standard nitride PECVD process is that the nitride film is known to react with a top surface of the copper layer during the deposition process and will consequently alter the electrical properties of the copper. In particular, the copper and nitride reaction is shown to substantially increase the copper line resistance, which in turn will delay signal transmission between devices. Slow signal transmission is not favored in most semiconductor devices, particularly in high speed, high density integrated circuits. Furthermore, high speed integrated circuits generally require conductors with low electrical resistance so as to facilitate current flow and signal transmission. Therefore, a reduction in copper line resistance is not only desirable but necessary in light of the constant demand for integrated circuits with higher speed and increased device density.
Hence, from the foregoing, it will be appreciated that there is a need for a process of depositing a non-conductive barrier layer so that any increase in the electrical resistance of the underlying conductive wiring or contact is reduced. To this end, there is a particular need for a process of depositing a non-conductive barrier layer wherein the barrier layer will not unfavorably increase the copper line resistance.